Selected Papers of the "22nd International Conference on Concurrency Theory" CONCUR 2011

2011

Editors: J.-P. Katoen and B. König

This special issue contains selected papers presented at the 22nd Conference on Concurrency Theory (CONCUR 2011) held in Aachen, Germany, September 6-9, 2011. The purpose of the CONCUR conference is to bring together researchers, developers, and students in order to advance the theory of concurrency and promote its applications. The conference invites submissions in the areas of semantics, logics, verification, and analysis of concurrent systems.

The 2011 edition of the conference attracted 94 submissions, from which 32 papers were selected for presentation at the conference. Based on the ranking of the papers by the program committee and the opinion of expert reviewers we selected five papers which reflect the high quality of the conference and represent a wide range of topics. We would like to thank the authors for their excellent submissions and we are happy to present the following contributions:

  • Vector Addition System Reversible Reachability Problem Jerome Leroux;
  • Coarse abstractions make Zeno behaviours difficult to detect Frederic Herbreteau and B. Srivathsan;
  • Bisimulations Meet PCTL Equivalences for Probabilistic Automata Lei Song, Lijun Zhang and Jens Chr. Godskesen;
  • Static Livelock Analysis in CSP Joel Ouaknine, Hristina Palikareva, Bill Roscoe and James Worrell;
  • Connector algebras for C/E and P/T nets interactions Roberto Bruni, Hernan Melgratti, Ugo Montanari, Pawel Sobocinski.

Joost-Pieter Katoen and Barbara König

Guest Editors and PC Co-Chairs of CONCUR 2011


1. Vector Addition System Reversible Reachability Problem

Jérôme Leroux.
The reachability problem for vector addition systems is a central problem of net theory. This problem is known to be decidable but the complexity is still unknown. Whereas the problem is EXPSPACE-hard, no elementary upper bounds complexity are known. In this paper we consider the reversible reachability problem. This problem consists to decide if two configurations are reachable one from each other, or equivalently if they are in the same strongly connected component of the reachability graph. We show that this problem is EXPSPACE-complete. As an application of the introduced materials we characterize the reversibility domains of a vector addition system.

2. Coarse abstractions make Zeno behaviours difficult to detect

Frédéric Herbreteau ; B Srivathsan.
An infinite run of a timed automaton is Zeno if it spans only a finite amount of time. Such runs are considered unfeasible and hence it is important to detect them, or dually, find runs that are non-Zeno. Over the years important improvements have been obtained in checking reachability properties for timed automata. We show that some of these very efficient optimizations make testing for Zeno runs costly. In particular we show NP-completeness for the LU-extrapolation of Behrmann et al. We analyze the source of this complexity in detail and give general conditions on extrapolation operators that guarantee a (low) polynomial complexity of Zenoness checking. We propose a slight weakening of the LU-extrapolation that satisfies these conditions.

3. Bisimulations Meet PCTL Equivalences for Probabilistic Automata

Lei Song ; Lijun Zhang ; Jens Chr. Godskesen ; Flemming Nielson.
Probabilistic automata (PAs) have been successfully applied in formal verification of concurrent and stochastic systems. Efficient model checking algorithms have been studied, where the most often used logics for expressing properties are based on probabilistic computation tree logic (PCTL) and its extension PCTL^*. Various behavioral equivalences are proposed, as a powerful tool for abstraction and compositional minimization for PAs. Unfortunately, the equivalences are well-known to be sound, but not complete with respect to the logical equivalences induced by PCTL or PCTL*. The desire of a both sound and complete behavioral equivalence has been pointed out by Segala in 1995, but remains open throughout the years. In this paper we introduce novel notions of strong bisimulation relations, which characterize PCTL and PCTL* exactly. We extend weak bisimulations that characterize PCTL and PCTL* without next operator, respectively. Further, we also extend the framework to simulation preorders. Thus, our paper bridges the gap between logical and behavioral equivalences and preorders in this setting.

4. Connector algebras for C/E and P/T nets' interactions

Roberto Bruni ; Hernan Melgratti ; Ugo Montanari ; Pawel Sobocinski.
A quite flourishing research thread in the recent literature on component-based systems is concerned with the algebraic properties of different classes of connectors. In a recent paper, an algebra of stateless connectors was presented that consists of five kinds of basic connectors, namely symmetry, synchronization, mutual exclusion, hiding and inaction, plus their duals, and it was shown how they can be freely composed in series and in parallel to model sophisticated 'glues'. In this paper we explore the expressiveness of stateful connectors obtained by adding one-place buffers or unbounded buffers to the stateless connectors. The main results are: i) we show how different classes of connectors exactly correspond to suitable classes of Petri nets equipped with compositional interfaces, called nets with boundaries; ii) we show that the difference between strong and weak semantics in stateful connectors is reflected in the semantics of nets with boundaries by moving from the classic step semantics (strong case) to a novel banking semantics (weak case), where a step can be executed by taking some 'debit' tokens to be given back during the same step; iii) we show that the corresponding bisimilarities are congruences (w.r.t. composition of connectors in series and in parallel); iv) we show that suitable monoidality laws, like those arising when representing stateful connectors in the tile model, can nicely capture concurrency (in the sense of step semantics) aspects; and v) as […]

5. A Static Analysis Framework for Livelock Freedom in CSP

Joel Ouaknine ; Hristina Palikareva ; A. W. Roscoe ; James Worrell.
In a process algebra with hiding and recursion it is possible to create processes which compute internally without ever communicating with their environment. Such processes are said to diverge or livelock. In this paper we show how it is possible to conservatively classify processes as livelock-free through a static analysis of their syntax. In particular, we present a collection of rules, based on the inductive structure of terms, which guarantee livelock-freedom of the denoted process. This gives rise to an algorithm which conservatively flags processes that can potentially livelock. We illustrate our approach by applying both BDD-based and SAT-based implementations of our algorithm to a range of benchmarks, and show that our technique in general substantially outperforms the model checker FDR whilst exhibiting a low rate of inconclusive results.